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Multichannel information processing has been used in data collection and analysis. Software tools allow data processing only after it enters the system, which can negatively affect the performance of the entire system. The operation result of the hardware pipeline processing based on FPGAs is the system load decrease while data processing. In this regard, the authors presented a pipeline adder, a specially designed system for acoustic detection, used in conjunction with a microphone array. The pipeline adder was implemented with the Verilog digital hardware description language. The designed algorithm output was compared with the solutions of the Vivado library re-designed, reusable blocks (IP-cores) in terms of to multi-bit multichannel computing. A structural diagram of a sequential transition from the serial interface inputs to summation results parallel outputs was presented including debugging and configuration blocks. Each IP-core operating capabilities were described. The IP-cores description fragments included in the adder structure were given. To verify the results, a simulation modeling method was used in the Modelsim HDL description digital simulator. The results confirmed the pipeline adder efficiency and suitability for the data processing systems usage. Ultimately, an efficient multichannel-data summing IP-core has been obtained without the system software part involvement, but with performance acceleration.

Key words: embedded systems, FPGA, pipelined computing, IP-core, embedded system performance
Published in: INTEGRATED RADIOELECTRONIC DEVICES
Bibliography link: Chekaldin I. R., Sukachev A. I., Dolgikh N. D., Sukacheva E. A., Timofeev D. V. Software-defined multichannel FPGA-based pipeline adder. Izv. vuzov. Elektronika = Proc. Univ. Electronics. 2026;31(4):472–482. (In Russ.). DOI: 10.24151/1561-5405-2026-31-4-472-482.WEPBNK
Financial source: the work has been supported by the Ministry of Science and Higher Education of the Russian Federation (project no. FZGM-2025-0002).

Ilya R. Chekaldin
Voronezh State Technical University, Russia, 394006, Voronezh, 20th Anniversary of October st., 84; JSC Research Institute of Electronic Technology, Russia, 394033, Voronezh, Starykh Bolshevikov st., 5

Alexander I. Sukachev
Voronezh State Technical University, Russia, 394006, Voronezh, 20th Anniversary of October st., 84

Nikita D. Dolgikh
Voronezh State Technical University, Russia, 394006, Voronezh, 20th Anniversary of October st., 84

Elena A. Sukacheva
Voronezh State Technical University, Russia, 394006, Voronezh, 20th Anniversary of October st., 84

Dmitry V. Timofeev
Voronezh State Technical University, Russia, 394006, Voronezh, 20th Anniversary of October st., 84

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DOI: 10.24151/1561-5405-2026-31-4-472-486
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